2015/12/23 期末上機考

module top; 

wire a, A, b, B, c, C, d, D, NF, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nor S1(a, A, A);

nor S2(b, B, B);

nor S3(c, C, C);

nor S4(d, D, D);

nor C1(F4, a, B, c, D);

nor C2(F2, b, d);

nor C3(F3, a, B, C, D);

nor C4(F1, A, B, c); 

nor o1(NF, F4, F2, F3, F1);

nor o2(F, NF, NF);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

123

module top; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand S1(a, A, B);

nand S2(b, B, B);

nand S3(c, C, C);

nand S4(d, D, D);

nand C1(F4, A ,c , d);

nand C2(F2, a, b, D);

nand C3(F3, B, c, d);

nand C4(F1, C, D); 

nand o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

12/2期末上機考-練習

module top;

wire A,B,C,D,F;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

not z1(a, A);
not z2(b, B);
not z3(c, C);
not z4(d, D);
and x1(F1, C, D);
and x2(F2, a, b, D);
and x3(F3, B, c, d);
and x4(F4, A, c, d);
or W(F, F1, F2, F3, F4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>3200)$stop;

endmodule

三位元加法器-行為

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

assign{c_out,sum}=a+b+c_in;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c; 

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

三位元加法器-結構

module top;

wire A0, B0,A1,B1,A2,B2,Cin0,Cout0,Cout1,Sum0,Sum1,Sum2,Cout2;

system_clock #200 clock1(Cin0); 

system_clock #200 clock2(A0);

system_clock #400 clock3(B0);

system_clock #800 clock2(A1);

system_clock #800 clock3(B1);

system_clock #1600 clock2(A2);

system_clock #1600 clock3(B2);

adder1 M1(Cout0, Sum0, A0, B0, Cin0);

adder1 M2(Cout1, Sum1, A1, B1, Cout0);

adder1 M3(Cout2, Sum2, A2, B2, Cout1);

endmodule

module adder1(Cout, Sum, A, B, Cin);

output Cout,Sum;

input A,B,Cin;

and I1 (AandB, A, B);

xor I2 (AxorB, A, B);

and I3 (And1, AxorB, Cin);

or I4 (Cout, AandB, And1);

xor I5 (Sum, AxorB, Cin);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>6400)$stop; 

endmodule

一位元加法器

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display("WRONG!");

              else

                $display("RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in); 

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule

module top; wire Cout, Sum, A, B, Cin; system_clock #400 clock1(Cin); system_clock #200 clock2(A); system_clock #100 clock3(B); adder1 M1(Cout, Sum, A, B, Cin); endmodule module adder1(Cout, Sum, A, B, Cin); output Cout,Sum; input A,B,Cin; and I1 (AandB, A, B); xor I2 (AxorB, A, B); and I3 (And1, AxorB, Cin); or I4 (Cout, AandB, And1); xor I5 (Sum, AxorB, Cin); endmodule module system_clock(clk); parameter PERIOD=100; output clk; reg clk; initial clk=0; always begin #(PERIOD/2) clk=~clk; end always@(posedge clk) if($time>1000)$stop; endmodule

四位元多工器10/21

module top; 

wire A0,A1,A2,A3,SEL,B0,B1,B2,B3,out0,out1,out2,out3,a1out, a2out, n1out ,a3out ,a4out ,a5out ,a6out,a7out,a8out;

system_clock #100 clock1(A1); 

system_clock #200 clock2(A0); 

system_clock #6400 clock3(SEL);

system_clock #400 clock4(B1);

system_clock #800 clock5(B0);

system_clock #1600 clock6(A2); 

system_clock #3200 clock7(B2);

system_clock #800 clock8(A3); 

system_clock #6400 clock9(B3);

and a1(a1out, A1, SEL);

and a2(a2out, A0, SEL);

not n1(n1out, SEL);

and a3(a3out, B1, n1out);

and a4(a4out, B0, n1out);

and a5(a5out, A2, SEL);

and a6(a6out, B2, n1out);

and a7(a7out, A3, SEL);

and a8(a8out, B3, n1out);

or o1(out1, a1out,a3out);

or o2(out0, a2out,a4out);

or O3(out2, a5out,a6out);

or o4(out3, a7out,a8out);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>12800)$stop; 

endmodule

三位元多工器 10/21

module top; 

wire A2,A1,A0,B2,B1,B0,SEL,OUT1,OUT2,OUT3;

system_clock #12800 clock7(A2); 

system_clock #6400 clock6(A1);

system_clock #3200 clock5(A0);

system_clock #1600 clock4(SEL);

system_clock #800 clock3(B2);

system_clock #400 clock2(B1);

system_clock #200 clock1(B0);

mux m1(OUT1,A1,B1,SEL);

mux m2(OUT2,A0,B0,SEL);

mux m3(OUT3,A2,B2,SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

一位元多工器

module top; 

wire SEL,A0,A1,B0,B1,OUT0,OUT1;

system_clock #100 clock1(B0); 

system_clock #200 clock2(B1);

system_clock #400 clock2(A0);

system_clock #800 clock2(A1);

system_clock #1600 clock2(SEL);

mux m1(OUT0,A1,B1,SEL);

mux m0(OUT1,A0,B0,SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

二位元多工器

module top;

wire A1, A0, B1, B0, OUT0, OUT1, OUT2, OUT3, OUT4, OUT5,OUT6;
system_clock #100 clock1(B0);
system_clock #200 clock2(B1);
system_clock #400 clock2(A0);
system_clock #800 clock2(A1);
system_clock #1600 clock2(SEL);

and a1(OUT0,A1,SEL);
and a2(OUT1,A0,SEL);
and a3(OUT2,B1,OUT6);
and a4(OUT3,B0,OUT6);
not n1(OUT6,SEL);
or o1(OUT4,OUT0,OUT2);
or o2(OUT5,OUT1,OUT3);

AND.OR.NO閘

邏輯閘電路

做一個電路真的不簡單，

先想整麼寫出這個電路，熟悉後再學如何把程式修改更簡潔

module top;

wire A, B, C, OUT1, OUT2;

system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(C);

and a1(OUT1, A, B);
and a2(OUT2, OUT1, C);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

波形圖片

好多人在比拚哦!!!

ICI數位IC認證

（數位IC設計能力鑑定）

          目的在於可評量各產官學研界提供之各數位電路 設計課程其考生的學習成效，以具備獨立完成數位電路邏輯設計流程與驗證之基本能力為 主要目的；更可進一步推廣數位電路實作，提升現有數位電路設計工程師之專業能力，提 供產業界優秀人才，降低企業訓練成本。

參考網址：http://www.cic.org.tw/icdesign/doc/IC_digital_FORM_104_v1.pdf

ARM的架構

ARM架構過去稱作進階精簡指令集機器（Advanced RISC Machine）

          ARM是一個32位元精簡指令集（RISC）中央處理器（processor）架構，其廣泛的使用在許多嵌入式系統設計。由於節約的特點，ARM處理器非常適用於行動通訊領域，符合其主要設計目標為低成本、高效能、低耗電的特性。

崁入式系統

          一種完全嵌入受控器件內部為特定應用設計的專用電腦系統，嵌入式系統通常執行的是帶有特定要求的預先定義的任務，由於嵌入式系統只針對一項特殊的任務，設計人員能夠對它進行優化，減小尺寸降低成本。