三位元加法器-結構

module top;

wire A0, B0,A1,B1,A2,B2,Cin0,Cout0,Cout1,Sum0,Sum1,Sum2,Cout2;

system_clock #200 clock1(Cin0); 

system_clock #200 clock2(A0);

system_clock #400 clock3(B0);

system_clock #800 clock2(A1);

system_clock #800 clock3(B1);

system_clock #1600 clock2(A2);

system_clock #1600 clock3(B2);

adder1 M1(Cout0, Sum0, A0, B0, Cin0);

adder1 M2(Cout1, Sum1, A1, B1, Cout0);

adder1 M3(Cout2, Sum2, A2, B2, Cout1);

endmodule

module adder1(Cout, Sum, A, B, Cin);

output Cout,Sum;

input A,B,Cin;

and I1 (AandB, A, B);

xor I2 (AxorB, A, B);

and I3 (And1, AxorB, Cin);

or I4 (Cout, AandB, And1);

xor I5 (Sum, AxorB, Cin);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>6400)$stop; 

endmodule