一位元加法器

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display("WRONG!");

              else

                $display("RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in); 

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule

module top; wire Cout, Sum, A, B, Cin; system_clock #400 clock1(Cin); system_clock #200 clock2(A); system_clock #100 clock3(B); adder1 M1(Cout, Sum, A, B, Cin); endmodule module adder1(Cout, Sum, A, B, Cin); output Cout,Sum; input A,B,Cin; and I1 (AandB, A, B); xor I2 (AxorB, A, B); and I3 (And1, AxorB, Cin); or I4 (Cout, AandB, And1); xor I5 (Sum, AxorB, Cin); endmodule module system_clock(clk); parameter PERIOD=100; output clk; reg clk; initial clk=0; always begin #(PERIOD/2) clk=~clk; end always@(posedge clk) if($time>1000)$stop; endmodule