2015/12/23 期末上機考

module top; 

wire a, A, b, B, c, C, d, D, NF, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nor S1(a, A, A);

nor S2(b, B, B);

nor S3(c, C, C);

nor S4(d, D, D);

nor C1(F4, a, B, c, D);

nor C2(F2, b, d);

nor C3(F3, a, B, C, D);

nor C4(F1, A, B, c); 

nor o1(NF, F4, F2, F3, F1);

nor o2(F, NF, NF);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule