四位元多工器10/21

module top; 

wire A0,A1,A2,A3,SEL,B0,B1,B2,B3,out0,out1,out2,out3,a1out, a2out, n1out ,a3out ,a4out ,a5out ,a6out,a7out,a8out;

system_clock #100 clock1(A1); 

system_clock #200 clock2(A0); 

system_clock #6400 clock3(SEL);

system_clock #400 clock4(B1);

system_clock #800 clock5(B0);

system_clock #1600 clock6(A2); 

system_clock #3200 clock7(B2);

system_clock #800 clock8(A3); 

system_clock #6400 clock9(B3);

and a1(a1out, A1, SEL);

and a2(a2out, A0, SEL);

not n1(n1out, SEL);

and a3(a3out, B1, n1out);

and a4(a4out, B0, n1out);

and a5(a5out, A2, SEL);

and a6(a6out, B2, n1out);

and a7(a7out, A3, SEL);

and a8(a8out, B3, n1out);

or o1(out1, a1out,a3out);

or o2(out0, a2out,a4out);

or O3(out2, a5out,a6out);

or o4(out3, a7out,a8out);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>12800)$stop; 

endmodule

三位元多工器 10/21

module top; 

wire A2,A1,A0,B2,B1,B0,SEL,OUT1,OUT2,OUT3;

system_clock #12800 clock7(A2); 

system_clock #6400 clock6(A1);

system_clock #3200 clock5(A0);

system_clock #1600 clock4(SEL);

system_clock #800 clock3(B2);

system_clock #400 clock2(B1);

system_clock #200 clock1(B0);

mux m1(OUT1,A1,B1,SEL);

mux m2(OUT2,A0,B0,SEL);

mux m3(OUT3,A2,B2,SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

一位元多工器

module top; 

wire SEL,A0,A1,B0,B1,OUT0,OUT1;

system_clock #100 clock1(B0); 

system_clock #200 clock2(B1);

system_clock #400 clock2(A0);

system_clock #800 clock2(A1);

system_clock #1600 clock2(SEL);

mux m1(OUT0,A1,B1,SEL);

mux m0(OUT1,A0,B0,SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

二位元多工器

module top;

wire A1, A0, B1, B0, OUT0, OUT1, OUT2, OUT3, OUT4, OUT5,OUT6;
system_clock #100 clock1(B0);
system_clock #200 clock2(B1);
system_clock #400 clock2(A0);
system_clock #800 clock2(A1);
system_clock #1600 clock2(SEL);

and a1(OUT0,A1,SEL);
and a2(OUT1,A0,SEL);
and a3(OUT2,B1,OUT6);
and a4(OUT3,B0,OUT6);
not n1(OUT6,SEL);
or o1(OUT4,OUT0,OUT2);
or o2(OUT5,OUT1,OUT3);

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