一位元多工器

module top; 

wire SEL,A0,A1,B0,B1,OUT0,OUT1;

system_clock #100 clock1(B0); 

system_clock #200 clock2(B1);

system_clock #400 clock2(A0);

system_clock #800 clock2(A1);

system_clock #1600 clock2(SEL);

mux m1(OUT0,A1,B1,SEL);

mux m0(OUT1,A0,B0,SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule