三位元加法器-行為

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

assign{c_out,sum}=a+b+c_in;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c; 

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

三位元加法器-結構

module top;

wire A0, B0,A1,B1,A2,B2,Cin0,Cout0,Cout1,Sum0,Sum1,Sum2,Cout2;

system_clock #200 clock1(Cin0); 

system_clock #200 clock2(A0);

system_clock #400 clock3(B0);

system_clock #800 clock2(A1);

system_clock #800 clock3(B1);

system_clock #1600 clock2(A2);

system_clock #1600 clock3(B2);

adder1 M1(Cout0, Sum0, A0, B0, Cin0);

adder1 M2(Cout1, Sum1, A1, B1, Cout0);

adder1 M3(Cout2, Sum2, A2, B2, Cout1);

endmodule

module adder1(Cout, Sum, A, B, Cin);

output Cout,Sum;

input A,B,Cin;

and I1 (AandB, A, B);

xor I2 (AxorB, A, B);

and I3 (And1, AxorB, Cin);

or I4 (Cout, AandB, And1);

xor I5 (Sum, AxorB, Cin);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>6400)$stop; 

endmodule

一位元加法器

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display("WRONG!");

              else

                $display("RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in); 

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule

module top; wire Cout, Sum, A, B, Cin; system_clock #400 clock1(Cin); system_clock #200 clock2(A); system_clock #100 clock3(B); adder1 M1(Cout, Sum, A, B, Cin); endmodule module adder1(Cout, Sum, A, B, Cin); output Cout,Sum; input A,B,Cin; and I1 (AandB, A, B); xor I2 (AxorB, A, B); and I3 (And1, AxorB, Cin); or I4 (Cout, AandB, And1); xor I5 (Sum, AxorB, Cin); endmodule module system_clock(clk); parameter PERIOD=100; output clk; reg clk; initial clk=0; always begin #(PERIOD/2) clk=~clk; end always@(posedge clk) if($time>1000)$stop; endmodule